Many electronic devices formed on an integrated circuit (IC), such as flash memory or electrically erasable programmable memory (EEPROM) for example, require voltage pulses with relatively large magnitudes for program and/or erase operations. In many electronic devices, these required voltage pulses are larger than a supply voltage powering the IC. For example, some flash memory chips often receive a supply voltage of about 5 volts on an external IC pin (many flash chips receive a supply voltage that is even lower than 5 volts), but require a “boosted” voltage of about −15 volts for erase operations.
Charge pumps are one type of circuit capable of delivering an output voltage with a “boosted” magnitude. To provide such a boosted output voltage, charge pumps include a number of switching elements arranged in series with one another, wherein charge transfer nodes are disposed between adjacent switching elements. Capacitors are coupled such that each capacitor has one plate coupled to a respective charge transfer node and has another plate coupled to one of at least two clock lines. Conventional charge pumps are regulated solely by monitoring an output voltage at an output node of the charge pump. In some negative charge pump implementations, for example, the charge pump is regulated so it continues to pump so long as the output voltage is higher than a target value. For example, if the target value is −16V, and the charge pump output is currently at −13V, the charge pump will continue to pump until the target value is reached. When the pump reaches the target voltage, the pump turns off. If the voltage output subsequently rises above the target voltage (e.g., rises to −10V), pumping commences again. Positive feedback continues in this manner such that the pump voltage output remains at or near the target voltage in a relatively constant manner.
Although such a regulation mechanism is adequate in some respects, difficulties can arise if the charge pump is inactive for an extended time period. For example, FIG. 1A shows a set of waveforms 100 that include an output voltage 102 provided by a conventional negative charge pump and a corresponding regulation signal 104. When the regulation signal 104 is low (e.g., at 108, 110), the charge pump is active; and when the regulation signal is high (e.g., at 112), the charge pump is inactive. Thus, during a first time interval 106 in which a load at the output of the charge pump is active (e.g., load is sourcing or sinking current), the charge pump is periodically activated (e.g., at 108 and 110) to keep the output voltage 102 at or near a target value 112 (e.g., −16 V). During a second time interval 114 in which the load is de-activated, the charge pump is continuously inactive and the output voltage continues to remain at or near the target value 112. Thus, FIG. 1A's chart illustrates proper charge pump functionality until the end of the second time interval 114.
Notably, however, at the end of the second time interval 114, there is an unexpected and rapid breakdown of the negative pump output at 116. For example, at 116 the output voltage 102 can rapidly go from the target output voltage 112 (e.g., −16V) to a less negative output voltage (e.g., −3V). Although the regulation signal 104 is quickly activated at 118 to try to alleviate the rapid voltage breakdown, the charge pump is unable to quickly pump the output voltage 102 back down to the target output voltage 112. This failure condition during time 120, can be due to a bipolar effect (such as latch-up, for example).
To illustrate one particular example of how latch-up can arise in a manner consistent with FIG. 1A's failure condition, FIG. 1B shows one switching element of a charge pump in the form of a triple well high voltage NMOS transistor 150. The transistor 150 is formed on a p-type substrate 152, and includes an n-type well 154, a p-type well 156, and n-type source/drain regions 158, 160. During normal operation, a gate voltage is selectively applied to a gate electrode 162 to form a conductive channel of charged carriers in a channel region 164 under the gate electrode 162, thereby coupling the source/drain regions 158, 160 to one another. However, when the charge pump is inactive for a long time period, the transistor 150 is correspondingly “open” throughout this time (i.e., gate voltage is continuously de-asserted throughout this long time period). Hence, the potential on the p-well 156 can begin to increase (e.g., by temperature dependent charging current of the reverse biased pn junction formed by pwell 156 and nwell 154) ultimately leading to a forward bias being generated over pwell/source or pwell/drain junction and causing turn-on of the vertical npn transistor formed by n-source/158/pwell 156/nwell 154 and/or n-drain 160/pwell 156/nwell 154 leading eventually to latch-up of the vertical 4-layer stack.
To remedy these shortcomings, the present disclosure provides improved charge pumps that limit failures due to latch-up.